Method of manufacturing optical devices and related improvements

ABSTRACT

There is disclosed a method of manufacturing of optical devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and the like. There is further disclosed Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices. According to the present invention there is provided a method of manufacturing an optical device ( 40 ), a device body portion ( 15 ) from which the device ( 40 ) is to be made including a Quantum Well Intermixing (QWI) structure ( 30 ), the method including the step of depositing a dielectric layer ( 51 ) on at least part of a surface of the device body portion ( 5 ) so as to introduce structural defects at least into a portion ( 53 ) of the device body portion ( 5 ) adjacent the dielectric layer ( 51 ). The structural defects substantially comprise “point” defects.

FIELD OF INVENTION

[0001] This invention relates to a method of manufacturing of opticaldevices, and in particular, though not exclusively, to manufacturingintegrated optical devices or optoelectronic devices, for example,semiconductor optoelectronic devices such as laser diodes, opticalmodulators, optical amplifiers, optical switches, and the like. Theinvention further relates to Optoelectronic Integrated Circuits (OEICs)and Photonic Integrated Circuits (PICs) including such devices.

BACKGROUND OF INVENTION

[0002] Quantum Well Intermixing (QWI) Well Intermixing (QWI) is aprocess which has been reported as providing a possible route tomonolithic optoelectronic integration. QWI may be performed in III-Vsemiconductor materials, eg Aluminium Gallium Arsenide (GaAs) Arsenide(AlGaAs) and Indium Gallium Arsenide (GaAs) Arsenide Phosphide(InGaAsP), which may be grown on binary substrates, eg Gallium Arsenide(GaAs) Arsenide (GaAs) or Indium Phosphide (InP). QWI alters theband-gap of an as-grown structure through interdiffusion of elements ofa Quantum Well Intermixing (QWI) and associated barriers to produce analloy of the constituent components. The alloy has a band-gap which islarger than that of the as-grown Quantum Well (QW). Any opticalradiation (light) generated within the Quantum Well (QW) where no QWIhas taken place can therefore pass through a QWI or “intermixed” regionof alloy which is effectively transparent to the said optical radiation.

[0003] Various QWI techniques have been reported in the literature. Forexample, QWI can be performed by high temperature diffusion of elementssuch as Zinc into a semiconductor material including a Quantum Well(QW).

[0004] QWI can also be performed by implantation of elements such assilicon into a Quantum Well (QW) semiconductor material. In such atechnique the implantation element introduces point defects in thestructure of the semiconductor material which are moved through thesemiconductor material inducing intermixing in the Quantum Well (QW)structure by a high temperature annealing step.

[0005] Such QWI techniques have been reported in “Applications ofNeutral Impurity Disordering in Fabricating Low-Loss Optical Waveguidesand Integrated Waveguide Devices”, Marsh et al, Optical and Quantum WellIntermixing (QWI) Electronics, 23, 1991, s941-s957, the content of whichis incorporated herein by reference.

[0006] A problem exists with such techniques in that although the QWIwill alter (increase) the band-gap of the semiconductor materialpost-growth, residual diffusion or implantation dopants can introducelarge losses due to the free carrier absorption coefficient of thesedopant elements.

[0007] A further reported QWI technique providing intermixing, isImpurity Free Vacancy Diffusion (IFVD) When performing IFVD the top caplayer of the III-V semiconductor structure is typically GaAs or IndiumGallium Arsenide (GaAs) Arsenide (InGaAs). Upon the top layer isdeposited a silica (S₁O₂) film. Subsequent rapid thermal annealing ofthe semiconductor material causes bonds to break within thesemiconductor alloy and Gallium Arsenide (GaAs) ions or atoms—which aresusceptible to silica (SiO₂)—to dissolve into the silica so as to leavevacancies in the cap layer. The vacancies then diffuse through thesemiconductor structure inducing layer intermixing, eg in the QuantumWell (QW) structure.

[0008] IFVD has been reported in “Quantitative Model for the Kinetics ofCompositional Intermixing in GaAs—AlGaAs Quantum Well Intermixing(QWI)—Confined Heterostructures”, by Helmy et al, IEEE Journal ofSelected Topics in Quantum Well Intermixing (QWI) Electronics, Vol 4, No4, July/August 1998, pp 653-660, the content of which is incorporatedherein by reference.

[0009] Reported QWI, and particularly IFVD methods, suffer from a numberof disadvantages, eg the temperature at which Gallium Arsenide (GaAs)out diffuses from the semiconductor material to the silica (SiO₂) film.

[0010] It is an object of at least one aspect of the present inventionto obviate or at least mitigate at least one of the aforementioneddisadvantages/problems in the prior art.

[0011] It is also an object of at least one aspect of the presentinvention to provide an improved method of manufacturing an opticaldevice using an improved QWI process.

SUMMARY OF INVENTION

[0012] According to a first aspect of the present invention, there isprovided a method of manufacturing an optical device, a device bodyportion from which the device is to be made including a Quantum WellIntermixing (QWI) structure, the method including the step of:

[0013] depositing a dielectric layer on at least part of a surface ofthe device body portion so as to introduce structural defects at leastinto a portion of the device body portion adjacent the dielectric layer.

[0014] The structural defects may include “point” defects.

[0015] Preferably, and advantageously, the dielectric layer is depositedby sputtering.

[0016] In a preferred embodiment the dielectric layer is deposited bysputtering using a diode sputterer.

[0017] The dielectric layer may beneficially substantially comprisesilica (SiO₂); or may comprise another dielectric material such asAluminium Oxide (Al₂O₃).

[0018] Preferably, the sputterer includes a chamber which may besubstantially filled with an inert gas such as Argon, preferably at apressure of around 2 μm of Hg, or a mixture of Argon and Oxygen, eg inthe proportion 90%/10%.

[0019] The step of depositing the dielectric layer may comprise part ofa Quantum Well Intermixing (QWI) process used in manufacture of thedevice.

[0020] The QWI process may comprise Impurity-Free Vacancy Disordering(IFVD).

[0021] Preferably, the method of manufacture also includes thesubsequent step of annealing the device body portion including thedielectric layer at an elevated temperature.

[0022] It has been surprisingly found that by depositing the dielectriclayer used in QWI techniques such as IFVD by sputtering, damage inducedpoint defects are introduced into the portion of the device body portionadjacent the dielectric cap; the portion may, for example, comprise atop or “capping” layer. It is believed that the damage arises due tobreakage of bonds in the capping layer before annealing, eg theapplication of thermal energy by rapid thermal annealing, therebyexpediting transfer of Gallium Arsenide (GaAs) from the capping layerinto the dielectric layer.

[0023] Preferably the method of manufacture also includes the precedingsteps of:

[0024] providing a substrate;

[0025] growing on the substrate:

[0026] a first optical cladding layer;

[0027] a core guiding layer including a Quantum Well

[0028] Intermixing (QWI) structure; and

[0029] a second optical cladding layer.

[0030] The first optical cladding layer, core guiding layer, and secondoptical cladding layer may be grown by Molecular Beam Epitaxy (MBE) orMetal Organic Chemical Vapour Deposition (MOCVD).

[0031] In a first embodiment the method may also include the step ofdefining a pattern in photoresist on a surface of the device bodyportion, depositing the dielectric layer and lifting off the photoresistso as to provide the dielectric layer on the said at least part of thesurface of the device body portion.

[0032] In said first embodiment, the method may also include the step ofdepositing a further dielectric layer on the surface of the device bodyand on a surface of the dielectric layer prior to annealing, preferablyby a technique other than sputtering, eg Plasma Enhanced Chemical VapourDeposition (PECVD).

[0033] In a second embodiment the method may include the steps ofdepositing the further dielectric layer and then depositing thedielectric layer.

[0034] In said first and second embodiments, the dielectric layer maycomprise an intermixing cap; the further dielectric layer may comprisean intermixing suppressing cap.

[0035] The thickness of the dielectric layer may be around 10 to a fewhundred nm.

[0036] The annealing step may occur at a temperature of around 700° C.to 1000° C. for around 0.5 to 5 minutes, and in one embodiment atsubstantially 800° C. for around 1 minute.

[0037] According to a second aspect of the present invention there isprovided a method of manufacturing an optical device, a device bodyportion from which the device is to be made including a Quantum WellIntermixing (QWI) structure, the method including the step of:

[0038] depositing a dielectric layer on at least part of a surface ofthe device body portion by sputtering.

[0039] According to a third aspect of the present invention there isprovided an optical device fabricated from a method according to eitherof the first or second aspects of the present invention.

[0040] The optical device may be an integrated optical device or anoptoelectronic device.

[0041] The device body portion may be fabricated in a III-Vsemiconductor materials system.

[0042] In one embodiment the III-V semiconductor materials system may bea Gallium Arsenide (GaAs) Arsenide (GaAs) based system, and maytherefore operate at a wavelength(s) of substantially between 600 and1300 nm. Alternatively, in a preferred embodiment the III-Vsemiconductor materials system may be an Indium Phosphide based system,and may therefore operate at a wavelength(s) of substantially between1200 and 1700 nm. The device body portion may be made at least partlyfrom Aluminium Gallium Arsenide (GaAs) Arsenide (AlGaAs), Indium GalliumArsenide (GaAs) Arsenide (InGaAs), Indium Gallium Arsenide (GaAs)Arsenide Phosphide, (InGaAsP), Indium Gallium Arsenide (GaAs), AluminiumArsenide (InGaAlAs) and/or Indium Gallium Arsenide (GaAs) AluminiumPhosphide (InGaAlP).

[0043] The device body portion may comprise a substrate upon which areprovided a first optical cladding layer, a core guiding layer, and asecond optical cladding layer.

[0044] Preferably the Quantum Well Intermixing (QWI) structure isprovided within the core guiding layer.

[0045] The core guiding layer, as grown, may have a smaller band-gap andhigher refractive index than the first and second optical claddinglayers.

[0046] According to a fourth aspect of the present invention, there isprovided an optical integrated circuit, optoelectronic integratedcircuit (OEIC), or photonic integrated circuit (PIC) including at leastone optical device according to the third aspect of the presentinvention.

[0047] According to a fifth aspect of the present invention, there isprovided a device body portion (“sample”) when used in a methodaccording to either the first or the second aspects of the presentinvention.

[0048] According to a sixth aspect of the present invention, there isprovided a wafer of material including at least one device body portionwhen used in a method according to either of the first or second aspectsof the present invention.

[0049] According to a seventh aspect of the present invention, there isprovided a sputtering apparatus when used in a method according to thesecond aspect of the present invention.

[0050] Preferably the sputtering apparatus is a diode sputterer.

[0051] According to an eighth aspect of the present invention, there isprovided use of a sputtering apparatus in a method according to eitherof the first or second aspects of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] An embodiment of the present invention will now be described, byway of example only, and with reference to the accompanying drawings,which are:

[0053]FIG. 1 a side view of a device body portion, as grown, for use ina method of manufacture of an optical device according to an embodimentof the present invention;

[0054]FIG. 2 a side view of an optical device according to an embodimentof the present invention manufactured from the device body portion ofFIG. 1;

[0055]FIG. 3 a schematic view of band-gap energies of a part of thedevice body portion of FIG. 1 the part comprising a core layer includinga Quantum Well Intermixing (QWI) therein;

[0056]FIG. 4 a schematic view similar to FIG. 3 of band-gap energies ofa corresponding part of the optical device of FIG. 2 when Quantum WellIntermixing (QWI);

[0057] FIGS. 5(a) to (f) a series of schematic side views of a devicebody portion during various steps of a method of manufacture of theoptical device of FIG. 2;

[0058]FIG. 6 a schematic representation of a diode sputterer apparatusfor use in deposition of a dielectric layer on the device body portionof FIGS. 5(a) to (f) during a dielectric layer deposition step shown inFIG. 5(c); and

[0059] FIGS. 7(a) and (b) more detailed schematic side views of thedevice body portion of FIGS. 5(a) to (f) before and after an annealingstep shown in FIG. 5(f).

DETAILED DESCRIPTION OF DRAWINGS

[0060] Referring initially to FIG. 1, there is shown a device bodyportion, generally designated 5, as grown, for use in a method ofmanufacture of an optical device according to a first embodiment of thepresent invention. The optical device is an integrated optical device oran optoelectronic device.

[0061] The device body portion 5 is suitably fabricated in a III-Vsemiconductor material system such as Gallium Arsenide (GaAs) Arsenide(GaAs), and therefore operates at a wavelength(s) of substantiallybetween 600 and 1300 nm, or alternatively, and beneficially, IndiumPhosphide (InP), and therefore operate at a wavelength(s) ofsubstantially between 1200 and 1700 nm. The device body portion 5 may bemade at least partly from Aluminium Gallium Arsenide (GaAs) Arsenide(AlGaAs), Indium Gallium Arsenide (GaAs) Arsenide (InGaAs), IndiumGallium Arsenide (GaAs) Arsenide Phosphide (InGaAsP), Indium AluminiumGallium Arsenide (GaAs) Arsenide (InGaAlsAs) and/or Indium GalliumArsenide (GaAs) Aluminium Phosphide (InGaAlP) In this described firstembodiment, the device body portion is made from AlGaAs.

[0062] The device body portion 5 may form part of a semiconductor wafer(see FIG. 6) together with a plurality of other possibly like opticaldevices which may be cleaved from the wafer after processing. The devicebody portion 5 comprises substrate 10 upon which is provided a firstoptical cladding layer 15, a core guiding layer 20, and a second opticalcladding layer 25. A Quantum Well Intermixing (QWI) structure 30,including at least one Quantum Well Intermixing (QWI) is provided withinthe core guiding layer 20, as grown. On the second optical claddinglayer 30 there is provided a capping layer 35.

[0063] As will be appreciated, the core guiding layer 20, as grown, hasa smaller band-gap and higher refractive index than the first and secondoptical cladding layer 15,25.

[0064] Referring now to FIG. 2, there is shown an optical device,generally designated 40, manufactured from the device body portion 5 ofFIG. 1, by a method which will be described in detail hereinafter. Ascan be seen from FIG. 2, the device 40 comprises an active region 45 anda passive region 50. In this embodiment the active region 45 comprises aQuantum Well Intermixing (QWI) Well (QUANTUM WELL (QW) amplifier.However, it should be understood that the active region 45 may in otherembodiments, comprise a laser, modulator switch, detector or like active(electrically controlled) optical device. Further, the passive region 50comprises a low-loss waveguide wherein the Quantum Well Intermixing(QWI) Well structure 30 has been at least partially removed by a QuantumWell Intermixing (QWI) Well Intermixing (QWI) technique, as willhereinafter be described in greater detail.

[0065] The device 40 has excellent alignment between the core layer 20waveguiding regions of the active region 45 and passive region 50, andhas a reflection coefficient between the active region 45 and passiveregion 50 which is substantially negligible (of the order of 10⁻⁶).Further, mode matching between the active region 45 and the passiveregion 50 is intrinsic to the device 40.

[0066] Typically, the substrate 10 is n-type doped to a firstconcentration, while the first cladding layer 15 is n-type doped to asecond concentration. Further, the core layer 20 is typicallysubstantially intrinsic, while the second cladding layer 25 is typicallyp-type doped to a third concentration. Further, the cap layer (orcontact layer) 35 is p-type doped to a fourth concentration. It will beappreciated by those skilled in the art, that the cap layer 35 andsecond cladding layer 25 may be etched into a ridge (not shown), theridge acting as an optical waveguide to confine optical modes within thecore layer 20, both within the optically active region 45 and theoptically passive region 50. Further, contact metallisations (not shown)may be formed on at least a portion of the top surface of the ridgewithin the optically active region 45, and also on an opposing surfaceof the substrate 10, as is known in the art.

[0067] It will further be appreciated that the device 40 may comprisepart of an optical integrated circuit, optoelectronic integrated circuit(OEIC), or photonic integrated circuit (PIC) which may comprise one ormore of such optical devices 40.

[0068] Referring now to FIG. 3, there is shown a schematicrepresentation of the band-gap energies of a Quantum Well Intermixing(QWI) Well 31 of the Quantum Well Intermixing (QWI) Well structure 30within the core layer 20 of the device body portion 5, as grown. As canbe seen from FIG. 3, the AlGaAs core layer 20 includes at least oneQuantum Well Intermixing (QWI) 31, with the Quantum Well Intermixing(QWI) structure 30 having a lower Aluminium content than the surroundingcore layer 20, such that the band-gap energy of the Quantum WellIntermixing (QWI) structure 30 is less than that of the surroundingAlGaAs core layer 20. The Quantum Well Intermixing (QWI) structure 30 istypically around 3 to 20 nm thick, and more typically around 10 nm inthickness.

[0069] Referring now to FIG. 4, there is shown a corresponding portion32 of the core layer 20 as in FIG. 3, but which has been Quantum WellIntermixing (QWI) so as to effectively increase the band-gap energy(meV) of the part 32 which corresponds to the Quantum Well Intermixing(QWI) 31 of the Quantum Well Intermixing (QWI) structure 30. QuantumWell Intermixing (QWI) Well Intermixing (QWI) therefore essentially“washes out” the Quantum Intermixing (QWI) structure 30 from the corelayer 20. The portion shown in FIG. 4 relates to the passive region 50of the device 40. As will be understood, optical radiation transmittedfrom or generated within the optically active region 45 of device 40will be transmitted through the low loss waveguide provided by theQuantum Well Intermixing (QWI) region 32 of the core layer 20 of thepassive region 50.

[0070] Referring now to FIGS. 5(a) to (f), there is illustrated a firstembodiment of a method of manufacturing an optical device 40 from adevice body portion 5, including a Quantum Well Intermixing (QWI)structure 30 according to the present invention, the method includingthe steps (see FIGS. 5(b) to (d)) of depositing a dielectric layer 51 onat least part of a surface 52 of the device body portion 5 so as tointroduce point defects into a portion 53 of the device body portion 5adjacent the dielectric layer 51.

[0071] The method of manufacture begins with the step of:

[0072] providing substrate 10, growing on the substrate 10 first opticalcladding layer 15, core guiding layer 20 including at least one QuantumWell Intermixing (QWI) 30, second optical cladding layer 25, and caplayer 35.

[0073] The first optical cladding layer 15, core guiding layer 20,second optical cladding layer 25, and cap layer 35 may be grown by knownsemiconductor epitaxial growth techniques such as Molecular Beam Epitaxy(MBE) Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD).Once the device body 5 has been grown—normally as part of a wafer (notshown) including a plurality of such device body portions 5—a patternmay be defined in Photo-Resist (PR) 55 on surface 52 of the device bodyportion 5. The dielectric layer 51 is deposited on the surface 52, andthe Photo-Resist 55 lifted off so as to leave the dielectric layer 51 onthe said at least part of the surface 52 of the device body portion 5.As can be seen from FIGS. 5(c) and 5(d), the dielectric layer 51deposited on at least part of the surface 52 of device body portion 5causes localised damage in region 53 of the cap layer 35, and introducespoint defects into the cap layer 35.

[0074] Referring briefly to FIG. 6, the dielectric layer 51 is depositedby sputtering, and in this embodiment the dielectric layer 51 isdeposited by sputtering using a diode sputterer apparatus, generallydesignated 65. The dielectric layer 51 substantially comprises Silica(SiO₂), but may in an a modification comprise another dielectricmaterial such as Aluminium Oxide (Al₂O₃). As can be seen from FIG. 6,the sputterer apparatus 65 includes a chamber 70 which in use issubstantially filled with an inert gas such as Argon which is preferablyprovided within the chamber 70 at a pressure of around 2 μm of Hg. Thesputterer 65 also comprises an RF source 75 connected to a cathode 80 ofthe diode sputterer 65. A Silica target 81 is provided on the cathode80, while the device body portion 5 (on wafer 82) is provided on theanode 85 of the diode sputterer 65. In use, as can be seen from FIG. 6,an Argon plasma 86 is generated between the cathode 80 and anode 85 withfirst and second dark spaces 90,95 being provided between the Silicatarget 81 and the Argon Plasma 86 and between the Argon Plasma and thedevice body portion 5, respectively.

[0075] The step of depositing the dielectric layer 51 comprises part ofa Quantum Well Intermixing (QWI) process used in the manufacture of thedevice 40, the QWI process comprising—in a preferred embodiment—anImpurity-Free Vacancy Disordering (IFVD) technique. It has beensurprisingly found that by depositing the dielectric layer 51 used inQWI techniques such as IFVD by sputtering using the sputterer 65, damageinduced defects are introduced into the portion 53 of the device bodyportion 5 adjacent dielectric cap 51; the portion 53 in this casecomprising part of the cap layer 35. It is believed that the damagebreaks bonds in the cap layer 35 prior to annealing (which willhereinafter be described), eg the application of thermal energy by rapidthermal annealing, thereby expediting the transfer of Gallium Arsenide(GaAs) from the cap layer 35 into the dielectric layer 51.

[0076] The dielectric layer 51 is typically between 10 to 1000 nm, andtypically 300 nm in thickness. The method of manufacture includes afurther step as shown in FIG. 5(e) of depositing further dielectriclayer 60 on the surface 52 of device body 5 and on a surface of thedielectric layer 51 prior to annealing. The further dielectric layer 60is deposited by a technique other than diode sputtering, and preferablyby a technique other than sputtering per se, eg Plasma Enhanced ChemicalVapour Deposition (PECVD).

[0077] The dielectric layer 51 therefore comprises an intermix caplayer, while the further dielectric layer 60 comprises an intermixsuppressing cap layer. The intermix suppressing cap layer is used toprotect the surface 52 from Arsenic desorption. The method will workwithout the intermix suppressing cap layer however; the quality of thesurface 52 may not be so good.

[0078] As shown in FIG. 5(f), subsequent to deposition of the furtherdielectric layer 60, the device body portions including the dielectriclayer 51 and further dielectric layer 60 are annealed at an elevatedtemperature. The annealing stage comprises a rapid thermal annealingstage, the annealing temperature being around 70020 C. to 1000° C. foraround 0.5 to 5 minutes, and in one implementation, at substantially800° C. for substantially 1 minute.

[0079] The action of the annealing step of FIG. 5f) is illustrateddiagrammatically in FIGS. 7(a) and (b). As can be seen from FIGS. 7(a)and (b), the annealing step causes “out diffusion” of Gallium Arsenide(GaAs) from the cap layer 35 to the intermixing cap, ie dielectric layer51. However, portions of the cap layer 35 below the suppressing cap, iefurther dielectric layer 60, are not subject to Gallium Arsenide (GaAs)“out-diffusion”. The portions of the cap layer 35 which lie within anarea of the intermixing cap, ie dielectric cap 51, are subject toout-diffusion of Gallium Arsenide (GaAs) as shown in FIG. 7(b). Theout-diffusion of Gallium Arsenide (GaAs) leaves vacancies behind whichvacancies migrate from the cap layer 35, through the second claddinglayer 25, and into the core layer 20, and hence to the Quantum WellIntermixing (QWI) structure(s) 30, thereby changing the effectiveband-gap of the Quantum Well Intermixing (QWI) structure 30, andeffectively washing-out the Quantum Well Intermixing (QWI) of theQuantum Well Intermixing (QWI) structure 30 below the intermixing caplayer.

[0080] It will be appreciated that the intermixing cap, ie dielectriclayer 51, is provided within the area of the passive region 50 to beformed in device 40, while the suppressing cap, ie further dielectriclayer 60, is provided on the device body portion 5 in areas such as theoptically active region 45 to be formed on the device 5, which areas arenot to be Quantum Well Intermixing (QWI).

[0081] Once the device body portion 5 has been processed to the stage ofFIG. 5(f), and annealed, the dielectric layer 51 and further dielectriclayer 60 may be removed by conventional methods, eg wet or dry etching.

EXAMPLE

[0082] There now follows an example which illustrates a typical band-gapshift which can be obtained using IFVD in a method of manufacturing anoptoelectronic device according to the present invention in a longwavelength aluminium alloy such as Indium Aluminium Gallium Arsenide(GaAs) Arsenide, (InAlGaAs), grown on an Indium Phosphide (InP)substrate.

[0083] The dielectric layer 51 deposition requires a sputter chamber 70configured in a diode configuration with a cathode/anode (plate)separation of the order to 100 mm. The cathode 80 and anode 85 are eachconfigured as substantially four inch circular plates. The gas used inthis example for sputter deposition is typically Argon, but othersuitable inert gases may be used, and also small amounts of Oxygen maybe added to the Argon Plasma 86, eg approximately 10% by volume, toimprove the stoichiometry of the deposited dielectric layer 51. Thedielectric material used in the method is typically Silica (SiO₂), butother dielectric materials such as Aluminium Oxide (Al₂O₃) can be used.It has been found that a preferred pressure in the chamber 70 for themethod is around 2 μm of Hg. For power values shown in Table 1 below, atwo minute deposition was carried out of the dielectric layer 45 on to asemiconductor wafer, including at least one device body portion 5. Theresultant dielectric film thickness was from 10 to a few hundred nm. Theband-gap shift figures in Table 1 illustrate the band-gap shift in theQuantum Well (QW) structure 30 for an anneal at a temperature of 800° C.for a time of 1 minute. TABLE 1 Deposition Conditions Band-Gap Shift(nm) PECVD (SiO₂) 1 300 watts sputtered (SiO₂) 12 500 watts sputtered(SiO₂) 21 700 watts sputtered (SiO₂) 38

[0084] as a better intermix cap than non-sputtered silica (SiO₂), andalso illustrates that the effectiveness of the sputtered silica (SiO₂)cap increases with increasing sputtering power.

[0085] In a second embodiment of a method of manufacturing an opticaldevice 40 according to the present invention, to process a wafer toproduce more than one band-gap a film of PECVD SiO₂ is deposited on tothe wafer to provide further dielectric layer 60. Photolithographytechniques are then used to delineate a pattern on top of the PECVDSiO₂. Either wet or dry etching can then be used to transfer the patterninto the PECVD (SiO₂).

[0086] Patterned photoresist (PR) is then left on top of the patternedPECVD (SiO₂), and the sample/wafer is then placed into the sputteringapparatus 65 for deposition of the dielectric layer 51. After depositionthe sample is immersed in acetone and the sputtered SiO₂ on thephotoresist is removed in a “lift-off” process.

[0087] A rapid thermal anneal is now performed at a suitable temperature(700-1000° C.) for the required period of time (0.5-5 min). This enablesthe point defects generated at the surface 52 to propagate through thedevice body portion 5 and cause interdiffusion of the elements.

[0088] It will be appreciated that the embodiment of the inventionhereinbefore described are given by way of example only, and are notmeant to limit the scope thereof in any way.

[0089] It should be particularly understood that the damage induced inthe semiconductor device body portion 5 adjacent to the sputtereddielectric layer 57 is believed to arise from radiation in the form ofsecondary electrons, soft x-rays and/or also from bombardment of ions.The damage to the surface 50 of the semiconductor device body portion 5or wafer 82, can be introduced by various means in the sputteringapparatus 65, an effective method being to use a diode configuration inthe deposition chamber 70. Using the diode configuration has beenunexpectedly found to permit more radiation damage to the device bodyportion 5 (or “sample”) than in the more usual magnetron machinearrangement wherein magnets create a high local field which it isbelieved stop particles travelling from the dielectric target 81 to thedevice body portion 5 provided on the wafer 82 of semiconductormaterial.

[0090] It will further be appreciated that an optical device accordingto the present invention may include a waveguide such as a ridge orburied heterostructure or indeed any other suitable waveguide.

[0091] It will also be appreciated that the Quantum Well Intermixing(QWI) regions may comprise optically active device(s).

[0092] Further, it will be appreciated that sequential processingincluding using several RF powers may be used to provide a device withseveral different QWI band-gaps.

1. A method of manufacturing an optical device, a device body portionfrom which the device is to be made including a Quantum Well Intermixing(QWI) structure, the method including the step of: depositing adielectric layer on at least part of a surface of the device bodyportion so as to introduce structural defects at least into a portion ofthe device body portion adjacent the dielectric layer.
 2. A method ofmanufacturing an optical device as claimed in claim 1, wherein thestructural defects substantially comprise point defects.
 3. A method ofmanufacturing an optical device as claimed in claim 1, wherein thedielectric layer is deposited by sputtering.
 4. A method ofmanufacturing an optical device as claimed in claim 1, wherein thedielectric layer is deposited by sputtering using a diode sputterer. 5.A method of manufacturing an optical device as claimed in claim 1,wherein the dielectric layer is selected from Silica (SiO₂) andAluminium Oxide (Al₂O₃).
 6. A method of manufacturing an optical deviceas claimed in claim 4, wherein the sputterer includes a chamber which issubstantially filled with an inert gas.
 7. A method of manufacturing anoptical device as claimed in claim 6, wherein the inert gas is selectedfrom Argon and a mixture of Argon and Oxygen.
 8. A method ofmanufacturing an optical device as claimed in claim 1, wherein the stepof depositing the dielectric layer comprises part of a Quantum WellIntermixing (QWI) Well Intermixing (QWI) process used in manufacture ofthe device.
 9. A method of manufacturing an optical device as claimed inclaim 8, wherein the QWI process comprises Impurity-Free VacancyDisordering (IFVD).
 10. A method of manufacturing an optical device asclaimed in claim 8, wherein the method of manufacture also includes thesubsequent step of annealing the device body portion including thedielectric layer at an elevated temperature.
 11. A method ofmanufacturing an optical device as claimed in claim 1, wherein themethod of manufacture also includes th e preceding steps of: providing asubstrate; growing on the substrate: a first optical cladding layer; acore guiding layer including a Quantum Well Intermixing (QWI) Wellstructure; and a second optical cladding layer.
 12. A method ofmanufacturing an optical device as claimed in claim 11, wherein thefirst optical cladding layer, core guiding layer, and second opticalcladding layer are grown by a growth technique selected from: MolecularBeam Epitaxy (MBE) Epitaxy (MBE) and Metal Organic Chemical VapourDeposition (MOCVD).
 13. A method of manufacturing an optical device asclaimed in claim 1, wherein the method also includes the step ofdefining a pattern in photoresist on a surface of the device bodyportion, depositing the dielectric layer and lifting off the photoresistso as to provide the dielectric layer on the said at least part of thesurface of the device body portion.
 14. A method of manufacturing anoptical device as claimed in claim 13, wherein the method also includesthe step of depositing a further dielectric layer on the surface of thedevice body and on a surface of the dielectric layer prior to annealing,the further dielectric layer being deposited by a technique other thansputtering.
 15. A method of manufacturing an optical device as claimedin claim 14, wherein the other technique comprises Plasma EnhancedChemical Vapour Deposition (PECVD).
 16. A method of manufacturing anoptical device as claimed in claim 1, wherein the method includes thesteps of depositing a further dielectric layer and then depositing thedielectric layer.
 17. A method of manufacturing an optical device asclaimed in claim 13, wherein the dielectric layer comprises anintermixing cap and further dielectric layer comprises an intermixingsuppressing cap.
 18. A method of manufacturing an optical device asclaimed in claim 1, wherein the thickness of the dielectric layer isaround 10 to a few hundred nm.
 19. A method of manufacturing an opticaldevice as claimed in claim 10, wherein the annealing step occurs at atemperature of around 700° C. to 1000° C. for around 0.5 to 5 minutes.20. A method of manufacturing an optical device, a device body portionfrom which the device is to be made including a Quantum Well Intermixing(QWI) Well (QUANTUM WELL (QW) structure, the method including the stepof: depositing a dielectric layer on at least part of a surface of thedevice body portion by sputtering.
 21. An optical device fabricated froma method according to either of claim 1 or
 20. 22. An optical device asclaimed in claim 21, wherein the optical device is selected from anintegrated optical device and an optoelectronic device.
 23. An opticaldevice as claimed in claim 21, wherein the device body portion isfabricated in a III-V semiconductor materials system.
 24. An opticaldevice as claimed in claim 21, wherein the III-V semiconductor materialssystem is a Gallium Arsenide (GaAs) Arsenide (GaAs) based system and thedevice operates at a wavelength(s) of substantially between 600 and 1300nm.
 25. An optical device as claimed in claim 21, wherein the III-Vsemiconductor materials system is an Indium Phosphide based system andthe device operates at a wavelength(s) of substantially between 1200 and1700 nm.
 26. An optical device as is claimed in claim 23, wherein thedevice body portion is made at least partly from Aluminium GalliumArsenide (GaAs) Arsenide (AlGaAs), Indium Gallium Arsenide (GaAs)Arsenide (InGaAs), Indium Gallium Arsenide (GaAs) Arsenide Phosphide,(InGaAsP), Indium Gallium Arsenide (GaAs) Aluminium Arsenide (InGaAlAs)and/or Indium Gallium Arsenide (GaAs) Aluminium Phosphide (InGaAlP). 27.An optical device as claimed in claim 21, wherein the device bodyportion comprises a substrate upon which are provided a first opticalcladding layer, a core guiding layer, and a second optical claddinglayer.
 28. An optical device as claimed in claim 27, wherein the QuantumWell Intermixing (QWI) Well (QUANTUM WELL (QW) structure is providedwithin the core guiding layer.
 29. An optical device as claimed in claim27, wherein the core guiding layer, as grown, has a smaller band-gap andhigher refractive index than the first and second optical claddinglayers.
 30. An optical integrated circuit, optoelectronic integratedcircuit (OEIC), or photonic integrated circuit (PIC) including at leastone optical device according to claim
 21. 31. A device body portion whenused in a method according to either of claim 1 or
 20. 32. A wafer ofmaterial including at least one device body portion when used in amethod according to either of claim 1 or
 20. 33. A sputtering apparatuswhen used in a method according to claim
 20. 34. A sputtering apparatusas claimed 33, wherein the sputtering apparatus is a diode sputterer.35. Use of a sputtering apparatus in a method according to either ofclaim 4 or 20.